1. Field of the Invention
This invention relates generally to mode setting circuits for memory devices, and more particularly to a mode setting circuit having reduced power consumption.
2. Description of the Related Art
In integrated circuits such as memory devices, a variety of circuit components for performing different operations are fabricated in the integrated circuit. This provides flexibility for selecting an optimal operation mode. After a memory chip is manufactured, it is tested to determine what functions are available in the chip, what operating characteristics the chip has, as well as various defects. This information is used to determine what operating modes can be utilized with the chip. Mode setting circuits on the chip are then used to optimize the chip by activating operational circuits, deactivating defective circuits and in other ways configuring and fixing the available circuit components so as to optimize the chip.
Such mode setting circuits help reduce the design period and thereby reduce the cost of integrated circuits. Two well known techniques for fixing the specific operation modes of a chip are the use of laser cut fuses and electrically cut fuses. With either laser or electrical fuses, the mode setting operation is carried out by either blowing a fuse or maintaining it intact.
FIGS. 1 and 2 illustrate the construction and operation of a mode setting circuit for a control block for EDO (extended data-out) in a semiconductor memory device. The EDO control block of FIG. 1 generates an output signal that enables or disables the EDO mode in accordance with the state of the fuse in the mode setting circuit.
FIGS. 3 and 4 illustrate the construction and operation of a prior art mode setting circuit, respectively, using a laser fuse. Referring to FIG. 3, a laser fuse 11 is connected between a power supply Vdd and a node N11. A p-type depletion mode MOS transistor 12 has a channel connected between node N11 and a power supply ground terminal GND. The gate of transistor 12 is connected to GND, and the transistor is in a normally conductive state. A capacitor 13 is connected between node N11 and GND. An n-type MOS transistor 15 has a channel connected between node N11 and GND. The gate of transistor 15 is connected to the output terminal of an inverter 14 which has an input terminal connected to node N11. A NOR gate 16 has a first input terminal connected to the output terminal of the inverter 14 and a second input terminal coupled to receive an input signal .PHI.A. The output terminal of NOR gate is connected to the input terminal of an inverter 17 which has an output terminal that generates an output signal OUTA.
When laser fuse 11 is blown, depletion mode transistor 12 connects node N11 to GND and transistor 15 holds node N 11 at ground. The output signal OUTA is generated in response to the input signal .PHI.A and the state of the fuse. If laser fuse 11 is intact, node 11 remains high because it is connected to Vdd through fuse 11 which also charges capacitor 13. Thus, the input signal .PHI.A determines the logic level of the output signal OUTA. When the fuse is intact, the output signal OUTA is low when .PHI.A is low, and OUTA is high when .PHI.A is high as shown in FIG. 4.
If fuse 11 is blown by laser cutting, node N11 is held at GND so as to maintain the output of NOR gate 16 at a low level regardless of the state of the input signal .PHI.A. That is, output signal OUTA is always high as shown in FIG. 4 when the fuse is cut.
However, since depletion mode transistor 12 is normally turned on, DC current flows from node N11 to ground resulting in excessive current consumption. The amount of current dissipated in a memory device having N mode setting circuits is N.times.IO, where IO is the amount of current flowing from node N11 to ground in the circuit of FIG. 3. Although the channel length of resistor 12 could be increased in order to reduce current consumption, this increases the layout size required for the mode setting circuit.
Accordingly, a need remains for a technique for reducing the power consumption of a mode setting circuit without increasing the layout size required for the circuit.